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19-3338; Rev 1; 3/05
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
General Description
The MAX1363/MAX1364 low-power, 12-bit, 4-channel analog-to-digital converters (ADCs) feature a digitally programmable window comparator with an interrupt output for automatic system-monitoring applications. Once configured, monitor mode automatically asserts an interrupt when any analog input exceeds the programmed upper or lower thresholds, without interaction to the host. The MAX1363/MAX1364 respond to the SMBusTM alert, allowing quick identification of the alarming device on a shared interrupt. A programmable delay between monitoring intervals lowers power consumption for reduced monitoring rates. In addition, the MAX1363/MAX1364 integrate an internal voltage reference, a clock, and a 1.7MHz, highspeed, I2CTM-compatible, 2-wire serial interface. The optimized interface allows a maximum conversion rate of 94.4ksps in normal mode while reading back the conversion results. Each of the four analog inputs is configurable for single-ended or fully differential operation and unipolar or bipolar operation. Two scan modes utilize on-chip random access memory (RAM) to allow eight conversions of a selected channel or scanning of a group of channels to reduce interface overhead. These devices operate from a single 2.7V to 3.6V (MAX1363) or 4.5V to 5.5V (MAX1364) supply and require only 436A at the maximum sampling rate of 133ksps in monitor mode and 670A at the maximum sampling rate of 94.4ksps. AutoShutdownTM powers down the devices between conversions, reducing supply current to less than 1A when idle. The full-scale analog-input range is determined by the internal reference or by an externally applied reference voltage ranging from 1V to VDD. The MAX1363 features a 2.048V internal reference, and the MAX1364 features a 4.096V internal reference. The MAX1363/MAX1364 are available in a 10-pin MAX(R) package and are specified over the extended (-40C to +85C) temperature range. For 10-bit applications, refer to the pin-compatible MAX1361/MAX1362 data sheet.
Features
Monitor Mode Programmable Lower/Upper Trip Threshold Alarm-Status Register Records Fault Events SMBus Alert Response Programmable Sampling Intervals 12-Bit, I2C-Compatible ADC 1 LSB INL, 1 LSB DNL 4-Channel Single-Ended or 2-Channel Fully Differential Inputs Software-Programmable Bipolar/Unipolar Conversions Fast Sampling Rate 94.4ksps While Continuously Reading Conversions 133ksps in Monitor Mode High-Speed, I2C-Compatible Serial Interface 100kHz/400kHz Standard/Fast Mode Up to 1.7MHz High-Speed Mode Six Available I2C Slave Addresses Single Supply 2.7V to 3.6V (MAX1363) 4.5V to 5.5V (MAX1364) Internal Reference 2.048V (MAX1363) 4.096V (MAX1364) External Reference: 1V to VDD Low Power 436A in Monitor Mode (133ksps) 670A at 94.4ksps 6A at 1ksps 0.5A in Power-Down Mode Small Package 10-Pin MAX
SMBus is a trademark of Intel Corporation. I2C is a trademark of Philips Corporation. Purchase of I2C components from Maxim Integrated Products, Inc. or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. AutoShutdown is a trademark of Maxim Integrated Products, Inc. MAX is a registered trademark of Maxim Integrated Products, Inc. Typical Operating Circuit and Pin Configuration appear at end of data sheet.
MAX1363/MAX1364
Applications
System Monitoring/Supervision Servers/Workstations High-Reliability Power Supplies Medical Instrumentation
Ordering Information/Selector Guide
PART MAX1363EUB MAX1363LEUB* MAX1363MEUB TEMP RANGE -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 10 MAX 10 MAX I2C SLAVE ADDRESS 0110100/0110101 0110010/0110011 SUPPLY VOLTAGE (V) 2.7 to 3.6 2.7 to 3.6
*Future product--contact factory for availability.
10 MAX 0110110/0110111 2.7 to 3.6 Ordering Information/Selector Guide continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
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4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
MAX1363/MAX1364
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V AIN0-AIN3, A0, REF to GND......................-0.3V to (VDD + 0.3V) SDA, SCL, INT to GND .............................................-0.3V to +6V Maximum Current Into Any Pin .........................................50mA Continuous Power Dissipation (TA = +70C) 10-Pin MAX (derate 5.6mW/C above +70C) ........444.4mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 3.6V (MAX1363), VDD = 4.5V to 5.5V (MAX1364), VREF = 2.048V (MAX1363), VREF = 4.096V (MAX1364), CREF = 0.1F, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Resolution Relative Accuracy Differential Nonlinearity Offset Error Offset-Error Temperature Coefficient Gain Error Gain Temperature Coefficient Channel-to-Channel Offset Matching Channel-to-Channel Gain Matching DYNAMIC PERFORMANCE (fIN(SINE-WAVE) = 10kHz, VIN(P-P) = VREF, fSAMPLE = 94.4ksps) Signal-to-Noise Plus Distortion Total Harmonic Distortion Spurious-Free Dynamic Range Full-Power Bandwidth Full-Linear Bandwidth CONVERSION RATE Conversion Time (Note 4) tCONV Internal clock External clock Internal clock, SCAN[1:0] = 01 Throughput Rate (Note 5) fSAMPLE External clock Monitor mode, SCAN[1:0] = 10 10.6 51 94.4 133 ksps 7.5 s SINAD THD SFDR SINAD > 57dB -3dB point Up to the 5th harmonic 70 -78 78 3.0 5.0 dB dB dB MHz MHz Relative to FSR (Note 3) Relative to FSR 0.3 0.1 0.1 0.3 4 INL DNL (Note 2) No missing codes SYMBOL CONDITIONS MIN 12 1 1 4 TYP MAX UNITS Bits LSB LSB LSB ppm/C LSB ppm/C LSB LSB
DC ACCURACY (fSAMPLE = 94.4ksps) (Note 1)
2
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4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX1363), VDD = 4.5V to 5.5V (MAX1364), VREF = 2.048V (MAX1363), VREF = 4.096V (MAX1364), CREF = 0.1F, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Track/Hold Acquisition Time Internal Clock Frequency Aperture Delay (Note 6) ANALOG INPUT (AIN0-AIN3) Input Voltage Range, Single Ended and Differential (Note 7) Input Multiplexer Leakage Current Input Capacitance INTERNAL REFERENCE (Note 8) Reference Voltage Reference-Voltage Temperature Coefficient REF Short-Circuit Current REF Source Impedance EXTERNAL REFERENCE REF Input Voltage Range REF Input Current Input High Voltage Input Low Voltage Input Hysteresis Input Current Input Capacitance Output Low Voltage INT OUTPUT Output Low Voltage INT Leakage Current Output Capacitance POWER REQUIREMENTS Supply Voltage VDD MAX1363 MAX1364 2.7 4.5 3.6 5.5 V ISINK = 3mA No faults detected 15 0.4 10 V A pF VREF IREF VIH VIL VHYST IIN CIN VOL ISINK = 3mA 15 0.4 0.1 x VDD 10 (Note 9) fSAMPLE = 94.4ksps 0.7 x VDD 0.3 x VDD 1 VDD 40 V A V V V A pF V 1.5 VREF TCVREF TA = +25C MAX1363 MAX1364 2.027 4.055 2.048 4.096 25 2 2.068 4.137 V ppm/C mA k Unipolar Bipolar ON/OFF-leakage current, VAIN_ = 0 or VDD CIN 0 -VREF / 2 0.01 22 VREF +VREF / 2 1 V A pF tAD External clock, fast mode External clock, high-speed mode SYMBOL CONDITIONS MIN 800 2.8 60 30 TYP MAX UNITS ns MHz ns
MAX1363/MAX1364
DIGITAL INPUTS/OUTPUTS (SCL, SDA, A0)
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4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
MAX1363/MAX1364
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX1363), VDD = 4.5V to 5.5V (MAX1364), VREF = 2.048V (MAX1363), VREF = 4.096V (MAX1364), CREF = 0.1F, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS fSAMPLE = Internal reference 133ksps, monitor mode External reference (Note 10) fSAMPLE = Internal reference 94.4ksps, external clock External reference MAX1363 fSAMPLE = 40ksps, internal clock fSAMPLE = 10ksps, internal clock fSAMPLE = 1ksps, internal clock Internal reference External reference Internal reference External reference Internal reference External reference MIN TYP 660 436 900 670 530 230 380 60 330 6 A 660 436 900 670 530 230 380 60 330 6 333 0.5 0.01 10 0.5 400 1.3 A LSB/V kHz s 1600 1350 1150 900 MAX 1600 1350 1150 900 UNITS
Supply Current
IDD
fSAMPLE = Internal reference 133ksps, monitor mode External reference (Note10) fSAMPLE = Internal reference 94.4ksps, external clock External reference fSAMPLE = MAX1364 40ksps, internal clock fSAMPLE = 10ksps, internal clock Internal reference External reference Internal reference External reference
fSAMPLE = Internal reference 1ksps, internal External reference clock Shutdown Current Power-Supply Rejection Ratio Serial Clock Frequency Bus Free Time Between a STOP (P) and a START (S) Condition PSRR fSCL tBUF Internal reference on Internal reference off Full-scale input (Note 11)
TIMING CHARACTERISTICS FOR FAST MODE (Figures 1a, 2)
4
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4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
MAX1363/MAX1364
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX1363), VDD = 4.5V to 5.5V (MAX1364), VREF = 2.048V (MAX1363), VREF = 4.096V (MAX1364), CREF = 0.1F, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Hold Time for START (S) Condition Low Period of the SCL Clock High Period of the SCL Clock Setup Time for a Repeated START Condition (Sr) Data Hold Time Data Setup Time Rise Time of Both SDA and SCL Signals, Receiving Fall Time of SDA Transmitting Setup Time for STOP (P) Condition Capacitive Load for Each Bus Line Pulse Width of Spike Suppressed TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Figures 1a, 2) (Note 12) Serial Clock Frequency Hold Time, Repeated START Condition (Sr) Low Period of the SCL Clock High Period of the SCL Clock Setup Time for a Repeated START Condition (Sr) Data Hold Time Data Setup Time Rise Time of SCL Signal, Current Source Enabled Rise Time of SCL Signal After Acknowledge Bit Fall Time of SCL Signal Rise Time of SDA Signal Fall Time of SDA Signal Setup Time for STOP (P) Condition Capacitive Load for Each Bus Line Pulse Width of Spike Suppressed fSCLH tHD, STA tLOW tHIGH tSU, STA tHD, DAT tSU, DAT tRCL tRCL1 tFCL tRDA tFDA tSU, STO CB (Notes 13, 14) 0 Measured from 0.3VDD to 0.7VDD Measured from 0.3VDD to 0.7VDD Measured from 0.3VDD to 0.7VDD Measured from 0.3VDD to 0.7VDD Measured from 0.3VDD to 0.7VDD (Note 14) (Note 13) (Note 13) 160 320 120 160 0 10 20 20 20 20 20 160 400 10 80 160 80 160 160 150 1.7 MHz ns ns ns ns ns ns ns ns ns ns ns ns pF ns SYMBOL tHD, STA tLOW tHIGH tSU, STA tHD, DAT tSU, DAT tR tF tSU, STO CB Measured from 0.3VDD to 0.7VDD Measured from 0.3VDD to 0.7VDD CONDITIONS MIN 0.6 1.3 0.6 0.6 0 100 0 0 0.6 400 50 300 300 900 TYP MAX UNITS s s s s ns ns ns ns s pF ns
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5
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
MAX1363/MAX1364
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX1363), VDD = 4.5V to 5.5V (MAX1364), VREF = 2.048V (MAX1363), VREF = 4.096V (MAX1364), CREF = 0.1F, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) Note 1: Devices configured for unipolar single-ended inputs. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain and offset have been calibrated. Note 3: Offset nulled. Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode. Note 5: The throughput rate of the I2C bus is limited to 94.4ksps. The MAX1363/MAX1364 can perform conversions up to 133ksps in monitor mode when not reading back results on the I2C bus. Note 6: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant. Note 7: The absolute input-voltage range for the analog inputs (AIN0-AIN3) is from GND to VDD. Note 8: When the internal reference is configured to be available at AIN3/REF (SEL[2:1] = 11), decouple AIN3/REF to GND with a 0.01F capacitor. Note 9: ADC performance is limited by the converter's noise floor, typically 300VP-P. Note 10: Maximum conversion throughput in internal clock mode when the data is not clocked out. Note 11: For the MAX1363, PSRR is measured as
N V (3.6V) - V (2.7V) x 2 - 1 FS FS VREF (3.6V - 2.7V)
[
]
and for the MAX1364, PSRR is measured as
N V (5.5V) - V (4.5V) x 2 - 1 FS FS VREF (5.5V - 4.5V) Note 12: CB = total capacitance of one bus line in pF. Note 13: fSCLH must meet the minimum clock low time plus the rise/fall times. Note 14: A master device must provide a data hold time for SDA (referred to VIL of SCL) to bridge the undefined region of SCL's falling edge.
[
]
Typical Operating Characteristics
(VDD = 3.3V (MAX1363), VDD = 5V (MAX1364), fSCL = 1.7MHz, external clock, fSAMPLE = 94.4ksps, single-ended, unipolar, TA = +25C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY vs. DIGITAL CODE
MAX1363/64 toc01
INTEGRAL NONLINEARITY vs. DIGITAL CODE
MAX1363/64 toc02
FFT PLOT
fSAMPLE = 94.4ksps fIN = 10kHz
MAX1363/64 toc03
0.5 0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0
1.0 0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
-60 -80 AMPLITUDE (dBc) -100 -120 -140 -160 -180
500 1000 1500 2000 2500 3000 3500 4000 DIGITAL OUTPUT CODE
0
500 1000 1500 2000 2500 3000 3500 4000 DIGITAL OUTPUT CODE
0
10
20
30
40
50
FREQUENCY (kHz)
6
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4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
Typical Operating Characteristics (continued)
(VDD = 3.3V (MAX1363), VDD = 5V (MAX1364), fSCL = 1.7MHz, external clock, fSAMPLE = 94.4ksps, single-ended, unipolar, TA = +25C, unless otherwise noted.)
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1363/64 toc05 MAX1363/64 toc04
MAX1363/MAX1364
SUPPLY CURRENT vs. TEMPERATURE
800 750 700 SUPPLY CURRENT (A) 650 600 550 500 450 400 350 300 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C) 0 2.7 EXTERNAL REFERENCE MAX1363 INTERNAL REFERENCE EXTERNAL REFERENCE INTERNAL REFERENCE MAX1364 SETUP BYTE EXT REF: 10111010 INT REF: 11011010 MAX1363 MAX1364 0.2 0.1 0.6
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
0.45 0.40 SUPPLY CURRENT (A) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 MAX1363 MAX1364
MAX1363/64 toc06
0.50
SDA = SCL = VDD 0.5 0.4 IDD (A) 0.3
3.2
3.7
4.2
4.7
5.2
-40 -25 -10
5
20
35
50
65
80
INPUT VOLTAGE (V)
TEMPERATURE (C)
AVERAGE SUPPLY CURRENT vs. CONVERSION RATE (EXTERNAL CLOCK)
800 750 700 650 600 550 500 450 400 350 300 250 200 0
MAX1363/64 toc07
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
MAX1363/64 toc08
NORMALIZED REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
1.00008 1.00006 VREF NORMALIZED 1.00004 1.00002 1.00000 0.99998 0.99996 MAX1363 NORMALIZED TO REFERENCE VALUE AT VDD = 3.3V 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 VDD (V) MAX1364 NORMALIZED TO REFERENCE VALUE AT VDD = 5V
MAX1363/64 toc09
1.0010 1.0008 1.0006 VREF NORMALIZED 1.0004 1.0002 1.0000 0.9998 0.9996 0.9994 0.9992 0.9990 MAX1363 NORMALIZED TO REFERENCE VALUE AT +25C MAX1364
A) INTERNAL REFERENCE ALWAYS ON B) EXTERNAL REFERENCE
1.00010
A
AVERAGE IDD (A)
B
0.99994 0.99992
10 20 30 40 50 60 70 80 90 100 CONVERSION RATE (ksps)
-40 -25
-10
5
20
35
50
65
80
0.99990
TEMPERATURE (C)
OFFSET ERROR vs. TEMPERATURE
MAX1363/64 toc10
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1363/64 toc11
GAIN ERROR vs. TEMPERATURE
0.9 0.8 GAIN ERROR (LSB) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
MAX1363/64 toc12
0 -0.1 -0.2 OFFSET ERROR (LSB) -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C)
0 -0.1 -0.2 OFFSET ERROR (LSB) -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0
1.0
2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 VDD (V)
-40 -25 -10
5
20
35
50
65
80
TEMPERATURE (C)
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4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
MAX1363/MAX1364
Typical Operating Characteristics (continued)
(VDD = 3.3V (MAX1363), VDD = 5V (MAX1364), fSCL = 1.7MHz, external clock, fSAMPLE = 94.4ksps, single-ended, unipolar, TA = +25C, unless otherwise noted.) MONITOR-MODE SUPPLY CURRENT GAIN ERROR vs. SUPPLY VOLTAGE vs. SPEED
MAX1363/64 toc13
0.9 0.8 GAIN ERROR (LSB) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2.7 3.2 3.7 4.2 VDD (V) 4.7 5.2
600 SUPPLY CURRENT (A) 500 INTERNAL REF 400 300 EXTERNAL REF 200 100 0 0 25 50 75 100 125
150
SPEED (ksps)
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 NAME AIN0 AIN1 AIN2 AIN3/VREF A0 INT SCL SDA GND VDD Analog Input Analog Input Analog Input Analog Input or Reference Input or Output. See Table 3. I2C Address Select Input. Connect to VDD or GND. See Table 1. Active-Low, Open-Drain Interrupt Output I2C Clock Input I2C Data Input/Output Ground Positive Supply Voltage. Bypass VDD to GND with a 0.1F capacitor. FUNCTION
Functional Diagram
VDD SDA SCL A0
CLK AIN0 AIN1 4:1 MUX AIN2 AIN3/ REF INT REF 12-BIT ADC
I2C INTERFACE
CONTROL
INT
TRIP THRESHOLDS
MAX1363/MAX1364
GND
8
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MAX1363/64 toc14
1.0
700
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
MAX1363/MAX1364
tR
tF
SDA
tSU.DAT tLOW
tHD.DAT tSU.STA
tHD.STA tSU.STO 9
tBUF
SCL
tSU.STA tR S
tHIGH tF Sr ACK P S
Figure 1a. F/S-Mode 2-Wire Serial-Interface Timing
tRDA tFDA
SDA
tSU.DAT tLOW 1 SCL
tHD.DAT tSU.STA
tHD.STA 9
tSU.STO
tHD.STA tRCL Sr
tHIGH tFCL Sr ACK tRCL1 P S
HS-MODE
F/S-MODE
Figure 1b. HS-Mode 2-Wire Serial-Interface Timing
Detailed Description
The MAX1363/MAX1364 4-channel ADCs use successive-approximation conversion techniques and fully differential input track/hold (T/H) circuitry to capture and convert analog signals to a serial 12-bit digital output. The MAX1363/MAX1364 feature a monitor mode with programmable trip thresholds and window comparator. The monitor function asserts an interrupt when any channel violates the programmed upper or lower thresholds. SMBus alert response allows the host microcontroller (C) to quickly identify which device caused the interrupt. A programmable delay between monitoring intervals lowers power consumption at lower monitor rates. The MAX1363/MAX1364 integrate an internal voltage reference and clock. The software configures the analog inputs for unipolar/bipolar and single-ended/fully differential operation. Integrated first-in/first-out (FIFO) allows conversion of all channels, or eight conversions
VDD IOL
SDA
VOUT 400pF IOH
Figure 2. Load Circuits
on a selected channel to reduce interface overhead. An I2C-compatible serial interface complies with standard, fast, and high-speed (1.7MHz) modes.
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4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
MAX1363/MAX1364
Power Supply
The MAX1363 (2.7V to 3.6V) and MAX1364 (4.5V to 5.5V) operate from a single supply and consume 670A (typ) at sampling rates up to 94.4ksps and 436A in monitor mode at 133ksps. The MAX1363 features a 2.048V internal reference, and the MAX1364 features a 4.096V internal reference. All devices can be configured for use with an external reference from 1V to V DD. Bypass V DD to GND using a 0.1F or greater ceramic capacitor for best performance.
Analog-Input and Track/Hold
The MAX1363/MAX1364 analog-input architecture contains an analog-input multiplexer (mux), fully differential T/H, comparator, and a fully differential switched capacitive digital-to-analog converter (DAC). Figure 3 shows the equivalent input circuit for the MAX1363/ MAX1364. In single-ended mode, the analog-input mux connects CT/H between the analog input selected by CS[3:0] and GND (see the Configuration/Setup Bytes (Write Cycle) section). In differential mode, the analog-input mux connects CT/H to the plus and minus analog inputs selected by CS[3:0]. During the acquisition interval, the T/H switches are in the track position, and CT/H charges to the analog-input signal. At the end of the acquisition interval, the T/H switches move to the hold position, retaining the charge on CT/H as a stable sample of the input signal. During the conversion, a switched capacitive DAC adjusts to restore the comparator input voltage to 0V within the limits of 12-bit resolution. This action requires
12 conversion clock cycles and is equivalent to transferring a charge of 11pF x (VIN+ - VIN-) from CT/H to the binary-weighted capacitive DAC, forming a digital representation of the analog-input signal. Use a low source impedance to ensure an accurate sample. A source impedance of up to 1.5k does not significantly degrade sampling accuracy. For larger source impedances, connect a 100pF capacitor from the analog input to GND or buffer the input. In internal clock mode, the T/H circuitry enters track mode on the eighth rising clock edge of the address byte (see the Slave Address section). The T/H circuitry enters hold mode on the falling clock edge of the acknowledge bit of the address byte (the ninth clock pulse). The conversions are then internally clocked, during which time the MAX1363/MAX1364 hold SCL low. In external clock mode, the T/H circuitry enters track mode after a valid address on the rising edge of the clock during the read bit (R/W = 1). Hold mode is entered on the rising edge of the second clock pulse during the shifting out of the 1st byte of the result. The next 12 clock cycles perform the conversions. The time required for the T/H circuitry to acquire an input signal is a function of the input sample capacitance. If the analog-input source impedance is high, the acquisition time constant lengthens and more time must be allowed between conversions. The acquisition time (tACQ) is the minimum time needed for the signal to be acquired. It is calculated by: tACQ 9 x (RSOURCE + RIN) x CIN
ANALOG-INPUT MUX AIN0
HOLD
REF CT/H
TRACK
AIN1
TRACK
AIN2
HOLD
TRACK
HOLD
CAPACITIVE DAC
VDD/2
AIN3/REF
TRACK
HOLD
TRACK
GND CT/H
CAPACITIVE DAC
HOLD
REF
MAX1363 MAX1364
Figure 3. Equivalent Input Circuit 10 ______________________________________________________________________________________
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
where RSOURCE is the analog-input source impedance, RIN = 2.5k, and CIN = 22pF. For internal clock mode, tACQ = 1.5 / fSCL, and for external clock mode tACQ = 2 / fSCL. Internal Reference The internal reference is 2.048V for the MAX1363 and 4.096V for the MAX1364. SEL1 of the setup byte controls whether AIN3/REF is used for an analog input or a reference. Decouple AIN3/REF to GND with a 0.1F capacitor and a 2k resistor in series with the capacitor. When AIN3/REF is configured as an internal reference output (SEL[1:0] = 11). See the Typical Operating Circuit. Once powered up, the reference remains on until reconfigured. Do not use the reference to supply current for external circuitry. External Reference The external reference ranges from 1V to VDD. For maximum conversion accuracy, the reference must deliver 40A and have an impedance of 500 or less. For noisy or high-output-impedance references, insert a 0.1F bypass capacitor to GND as close to AIN3/REF as possible.
MAX1363/MAX1364
Analog-Input Bandwidth
The MAX1363/MAX1364 feature input-tracking circuitry with a 5MHz small-signal bandwidth. The 5MHz input bandwidth makes it possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid high-frequency signals from aliasing into the frequency band of interest, use anti-aliasing filtering.
Analog-Input Range and Protection
Internal protection diodes clamp the analog inputs to VDD and GND. These diodes allow the analog inputs to swing from (GND - 0.3V) to (VDD + 0.3V) without causing damage to the device. For accurate conversions, the inputs must remain within 50mV below GND or above VDD.
Clock Modes
The clock mode determines the conversion clock and the data acquisition and conversion time. The clock mode also affects the scan mode. The state of the setup byte's INT/EXT clock bit determines the clock mode. At power-up, the MAX1363/MAX1364 default to internal clock mode (INT/EXT clock = 0). Internal Clock See the Configuration/Setup Bytes (Write Cycle) section. In internal clock mode (CLK = 0), the MAX1363/ MAX1364 use an internal oscillator for the conversion clock. The MAX1363/MAX1364 begin tracking the analog input after a valid address on the eighth rising edge of the clock. On the falling edge of the ninth clock, the analog signal is acquired and the conversion begins. While converting, the MAX1363/MAX1364 hold SCL low (clock stretching). After completing the conversion, the results are stored in internal memory. For scan-mode configurations with multiple conversions (see the Scan Modes section), all conversions happen in succession with each additional result stored in memory. Once all conversions are complete, the MAX1363/MAX1364 release SCL, allowing it to go high. The master can now clock the results out in the same order as the scan conversion. The converted results are read back in a FIFO sequence. If AIN3/REF is configured as a reference input or output, AIN3/REF is excluded from multichannel scan. If reading continues past the final result stored in memory, the pointer wraps around and points to the first result. Only the current conversion results are read from memory. The MAX1363/MAX1364 must be addressed with a read command to obtain new conversion results.
11
Single-Ended/Differential Input
The SE/DIF of the configuration byte configures the MAX1363/MAX1364 analog-input circuitry for singleended or differential input. In single-ended mode (SE/DIF = 1), the digital conversion results are the difference between the analog input selected by CS[3:0] and GND. In differential mode (SE/DIF = 0), the digital conversion results are the difference between the plus and the minus analog inputs selected by CS[3:0] (see Tables 5 and 6).
Unipolar/Bipolar
Unipolar mode sets the differential input range from 0 to VREF. A negative differential analog input in unipolar mode causes the digital output code to be zero. Selecting bipolar mode sets the differential input range to VREF / 2. The digital output code is binary in unipolar mode and two's complement in bipolar mode. (See the Transfer Functions section.) In single-ended mode the MAX1363/MAX1364 always operate in unipolar mode. The analog inputs are internally referenced to GND with a full-scale input range from 0 to VREF (Table 7).
Reference
SEL[2:0] of the setup byte controls the reference and the AIN3/REF configuration. When AIN3/REF is configured as a reference input or reference output (SEL1 = 1), differential conversions on AIN3/REF appear as if AIN3/REF is connected to GND. A single-ended conversion in scan mode on AIN3/REF is ignored by an internal limiter that sets the highest available channel at AIN2.
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4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
MAX1363/MAX1364
External Clock See the Configuration/Setup Bytes (Write Cycle) section. When configured for external clock mode (CLK = 1), the MAX1363/MAX1364 use SCL as the conversion clock. In external clock mode, the MAX1363/MAX1364 begin tracking the analog input on the ninth rising clock edge of a valid slave address byte. Two SCL clock cycles later, the analog signal is acquired and the conversion begins. Unlike internal clock mode, converted data is clocked out immediately in the format described in the Reading a Conversion (Read Cycle) section. The device continuously converts input channels dictated by the scan mode until given a not acknowledge (NACK). There is no need to readdress the device with a read command to obtain new conversion results. The conversion must complete in 1ms or droop on the T/H capacitor degrades conversion results. Use internal clock mode if the SCL clock period exceeds 60s. Use external clock mode for conversion rates from 40ksps to 94.4ksps. Use internal clock mode for conversions under 40ksps. Internal clock mode consumes less power. Monitor mode always uses internal clock mode.
in or out of the MAX1363/MAX1364 (8 bits and an ACK/NACK). The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is stable and high are considered control signals (see the START and STOP Conditions section). Both SDA and SCL remain high when the bus is not busy. START and STOP Conditions The master initiates a transmission with a START condition (S), which is a high-to-low transition on SDA while SCL is high. The master terminates a transmission with a STOP condition (P), which is a low-to-high transition on SDA while SCL is high (Figure 4). A repeated START condition (Sr) can be used in place of a STOP condition to leave the bus active and the mode unchanged (see the HS I2C Mode section). Acknowledge and Not-Acknowledge Conditions Data transfers are framed with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the master and the MAX1363/MAX1364 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (Figure 5). To generate a not-acknowledge condition, the receiver allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse, and leaves SDA high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of
Applications Section
Power-On Reset
The configuration and setup registers default to a single-ended, unipolar, single-channel conversion on AIN0 using the internal clock with VDD as the reference and AIN3/REF configured as an analog input. The memory contents are unknown at power-up (see the Software Description section).
I2C-Compatible 2-Wire Serial Interface
The MAX1363/MAX1364 use an I2C-compatible 2-wire interface consisting of a serial data line (SDA) and serial clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX1363/MAX1364 and the master at rates up to 1.7MHz. The master (typically a C) initiates data transfer on the bus and generates the SCL signal to permit data transfer. The MAX1363/ MAX1364 behave as I2C slave devices that transfer and receive data. SDA and SCL must be pulled high for proper I2C operation. This is typically done with pullup resistors (750 or greater). Series resistors (RS) are optional (see the Typical Operating Circuit section). The resistors protect the input architecture of the MAX1363/MAX1364 from high voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus signals. One bit transfers during each SCL clock cycle. A minimum of nine clock cycles is required to transfer a byte
12
S Sr P SDA
SCL
Figure 4. START and STOP Conditions
S
NOT ACKNOWLEDGE
SDA ACKNOWLEDGE SCL 1 2 8 9
Figure 5. Acknowledge Bits
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4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
MAX1363/MAX1364
SLAVE ADDRESS S 0 1 1 0 1 0 0 R/W ACK
SDA
SCL
1
2
3
4
5
6
7
8
9
Figure 6. MAX1363/MAX1364 Slave Address Byte
Table 1. I2C Slave Selection Table
A0 STATE Low High Low High Low High SUFFIX EUB EUB LEUB LEUB MEUB MEUB ADDRESS 0110100 0110101 0110010 0110011 0110110 0110111
recognizes its slave address, it is ready to accept or send data depending on the R/W bit (Figure 6). HS I2C Mode At power-up, the MAX1363/MAX1364 bus timing is set for fast mode (F/S mode, up to 400kHz I2C clock), which limits the conversion rate to approximately 22ksps. Switch to high-speed mode (HS mode, up to 1.7MHz I2C clock) to achieve conversion rates up to 94.4ksps. The MAX1363/MAX1364 convert up to 133ksps in monitor mode, regardless of I2C mode. If conversion results are unread, I2C bandwidth limitations do not apply (see the Monitor Mode section). Select HS mode by addressing all devices on the bus with the HS-mode master code 0000 1XXX (X = don't care). After successfully receiving the HS-mode master code, the MAX1363/MAX1364 issue a NACK, allowing SDA to be pulled high for one clock cycle (Figure 7). After the NACK, the MAX1363/MAX1364 operate in HS mode. Send a repeated START (Sr) followed by a slave address to initiate HS-mode communication. If the master generates a STOP condition, the MAX1363/ MAX1364 return to F/S mode. Use a repeated START condition (Sr) in place of a STOP condition to leave the bus active and the mode unchanged.
unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master reattempts communication at a later time. Slave Address The MAX1363/MAX1364 have a 7-bit I 2 C slave address. The slave address is selected using A0. The MAX1363/MAX1364 (EUB, MEUB, and LEUB) have three base address options, allowing up to six devices concurrently per I2C bus (see Table 1). The MAX1363/MAX1364 continuously wait for a START condition followed by its slave address. When the device
HS-MODE MASTER CODE S 0 0 0 0 1 X X X NACK Sr
SDA
SCL
F/S MODE
HS MODE
Figure 7. F/S-Mode to HS-Mode Transfer ______________________________________________________________________________________ 13
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
MAX1363/MAX1364
START CONDITION START
R/W BIT FROM THE MASTER ADDRESS FROM THE MASTER 0 A CONFIGURATION BYTE FROM THE MASTER A SETUP BYTE FROM THE MASTER A STOP
Figure 8. Example of Writing Setup and Control Bytes
START CONDITION START
R/W BIT FROM THE MASTER ADDRESS FROM THE MASTER 0 A SETUP BYTE FROM THE MASTER 1 A ALARM RESET, SCAN SPEED, BYTE FROM MASTER A
CH 0 LT [11:4] BYTE
A
CH 0 LT [3:0]; UT [11:8] BYTE
A
CH 0 UT [7:0] BYTE
A
CH 1 LT [11:4] BYTE
A
STOP
Figure 9. Example of Extended Setup Byte Writing
Table 2. Configuration Byte Format*
BIT 7(MSB) 6 5 4 3 2 NAME CONFIG SCAN1 SCAN0 CS3 CS2 CS1 The configuration byte always starts with 0. SCAN1, SCAN0 = [0,0], scans from channel 0 to the upper channel chosen by CS1, CS0. SCAN1, SCAN0 = [0,1], converts a single channel chosen by CS1, CS0 eight times. SCAN1, SCAN0 = [1,0] monitor mode monitors from channel 0 to the upper channel chosen by CS1, CS0. SCAN1, SCAN0 = [1,1], single channel conversion for the channel is chosen by CS0, CS1. CS3, CS2 = [1,1] enables readback of monitor-mode setup data. Selects the upper limit of the channel range used for the conversion sequence in scan modes SCAN = [0,0] and monitor modes SCAN = [1,0]. Selects the conversion channel when SCAN = [0,1] or when SCAN = [1,1]. (Tables 5 and 6) 1 = single-ended inputs. 0 = differential inputs. AIN0 and AIN1 form the first differential pair and AIN2 and AIN3 form the second differential pair. (See Tables 4 and 5.) Selects single-ended or differential conversions. In single-ended mode, input-signal voltages are referenced to GND. In differential mode, the voltage difference between two channels is measured. When single-ended mode is used, the MAX1363/MAX1364 perform unipolar conversions regardless of the UNI/BIP bit in the setup byte. (Table 7) DESCRIPTION
1
CS0
0
SE/DIF
*Power-on defaults: 0x01
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4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
Software Description
Configuration/Setup Bytes (Write Cycle)
A write cycle begins with the bus master issuing a START condition followed by 7 address bits and a write bit (R/W = 0). If the address byte is successfully received, the MAX1363/MAX1364 (slave) issue an ACK. The master then writes to the slave. If the most significant bit (MSB) is 1, the slave recognizes the received byte as the setup byte (Table 4). If the MSB is 0, the slave recognizes that byte as the configuration byte (Table 2). Write to the configuration byte before writing to the setup byte (Figure 8). If enabling RESET in the setup byte, rewrite the configuration byte after writing the setup byte, since RESET clears the contents of the configuration byte back to the power-up state. When the monitor-setup bit of the setup byte is set to 1, writing extends up to 13 bytes to clock in monitor-setup data. Terminate writing monitor-setup data at any time by issuing a STOP or repeated START condition. If the slave receives a byte successfully, it issues an ACK (Figure 9). Note: When operating in HS mode, a STOP condition returns the bus into F/S mode (see the HS I2C Mode section). 10ms to wake up. Therefore, power up the internal reference 10ms prior to conversion or leave the reference continuously powered. Wake-up is transparent when using an external reference or VDD as the reference. Automatic shutdown results in dramatic power savings, particularly at slow conversion rates with internal clock. For example, using an external reference at a conversion rate of 10ksps, the average supply current for the MAX1363 is 60A (typ) and drops to 6A (typ) at 1ksps. At 0.1ksps, the average supply current is just 1A. Table 3 shows AIN3/REF configuration and reference power-down state.
MAX1363/MAX1364
Scan Modes
SCAN1 and SCAN0 of the configuration byte set the scan-mode configuration. When configuring AIN3/REF for reference input or output (SEL0 = 1), AIN3/REF is excluded from a multichannel scan. The scanned results write to memory in the same order as the conversion. Start a conversion sequence by initiating a read with the desired scan mode. Read the results from memory in the order they were converted (see the Reading a Conversion (Read Cycle) section). Selecting channel scan mode [0,0] starts converting from channel 0 up to the channel chosen by CS1, CS0. Selecting channel scan mode [0,1] converts the channel selected by CS1, CS0 eight times and returns eight consecutive results. Selecting monitor mode [1,0] initiates a continuous conversion scan sequence from channel 0 to the channel selected by CS1, CS0. See the Monitor Mode section for more details. Selecting channel scan mode [1,1] performs a single conversion on the channel selected by CS1, CS0 and returns the result.
Automatic Shutdown
AutoShutdown occurs between conversions when the MAX1363/MAX1364 are idle. When operating in external clock mode, issue a STOP, NACK, or repeated START condition to place the devices in idle mode and benefit from automatic shutdown. A STOP condition is not necessary in internal clock mode for automatic shutdown because power-down occurs once all contents are written memory. Shutdown reduces supply current to less than 0.5A (external reference mode, typ) and 300A (internal reference mode, typ). When idle, the MAX1363/MAX1364 continuously wait for a START condition followed by their slave address. Upon reading a valid address byte, the MAX1363/ MAX1364 power up. The internal reference requires
Reading a Conversion (Read Cycle)
Initiate a read cycle to start a conversion sequence and to obtain conversion results. See the Scan Modes section for details on the channel-scan sequence. Read
Table 3. Reference Voltage and AIN3/REF Format
SEL1 0 0 1 1 1 1 SEL0 0 1 0 0 1 1 INT REF POWER-DOWN X X 0 1 0 1 REFERENCE VOLTAGE VDD External reference Internal reference Internal reference Internal reference Internal reference AIN3/REF Analog input Reference input Analog input Analog input Reference output Reference output INTERNAL REFERENCE STATE Always off Always off Always off Always on Always off Always on
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4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
MAX1363/MAX1364
Table 4. Setup-Byte Format*
BIT 7 (MSB) 6 5 NAME Setup REF/AIN SEL1 REF/AIN SEL0 INT REF Power Down INT/EXT Clock Setup byte always starts with 1. When [0,0], REF/AIN3 = AIN3, REF = VDD. When [0,1], REF/AIN3 = REF, apply external reference to REF. When [1,0], REF/AIN3 = AIN3, REF = internal reference. When [1,1], REF/AIN3 = REF, REF = internal reference. (Table 3) 1 = internal reference always powered up. 0 = internal reference always powered down. (Table 3) 0 = internal clock. 1 = external clock (MAX1363/MAX1364 use the SCL clock for conversions). 0 = unipolar. 1 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, analog signal in 0 to VREF range can be converted. In differential bipolar mode, input signal can range from -VREF / 2 to +VREF / 2. When single-ended mode is chosen, the SE/DIF bit of configuration byte overrides UNI/BIP, and conversions are performed in unipolar mode. 1 = no action. 0 = resets INT and configuration register. Setup register and channel trip thresholds are unaffected. 0 = no action. 1 = extends writing up to 13 bytes (104 bits) of alarm reset mask. Scans speed selection and alarm thresholds. See the Configuring Monitor Mode section. DESCRIPTION
4
3
2
UNI/BIP
1
Reset
0
Monitor Setup
*Power-on defaults: 0x82
Table 5. Channel Selection in SingleEnded Mode (SE/DIF = 1)
CS1 0 0 1 1 CS0 0 1 0 1 CH0 + + + + CH1 CH2 CH3
Table 7. SE/DIF and UNI/BIP Table
SE/DIF 0 0 1 1 UNI/BIP 0 1 0 1 MODE Differential inputs, unipolar Differential inputs, bipolar Single-ended inputs, unipolar Single-ended inputs, unipolar
Table 6. Channel Selection in Differential Mode (SE/DIF = 0)
CS1 0 0 1 1 CS0 0 1 0 1 CH0 + CH1 + + + CH2 CH3
cycles begin with the bus master issuing a START condition followed by 7 address bits and a read bit (R/W = 1). After successfully receiving the address byte, the MAX1363/MAX1364 (slave) issue an ACK. The master then reads from the slave. (See Figures 10-13.) The result is transmitted in 2 bytes. The 1st byte consists of a leading 1 followed by a 2-bit binary channel address tag, a 12/10 bit flag (1 for the MAX1363/ MAX1364), the first 4 bits of the data result, and the expected ACK from the master. The 2nd byte contains D7-D0. To read the next conversion result, issue an ACK. To stop reading, issue a NACK.
16
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4-Channel, 12-Bit System Monitors with Programmable
MAX1363/MAX1364
Table 8. Data Format
HIGH 1 CH1 0/1 CH0 0/1 1 12/1 0 0 = 10b 1 = 12b
START CONDITION ADDRESS START FROM THE MASTER
HIGH HIGH 1 1
DATA (MSB) 0/1
D8 0/1 ACK
D7 0/1
D6 0/1
D5 0/1
D4 0/1
D3 0/1
D2 0/1
D1 0/1
D0 0/1 ACK/ NACK
R/W 1 ACK 1, CH ADD, 10b/12b FLAG, RESULT (4 MSBs) tACQ ACK tCONV RESULT (8 LSBs) ACK STOP
Figure 10. Example of Reading the Conversion Result--External Clock Mode
R/W ADDRESS START FROM THE MASTER 1 ACK MAX1363/MAX1364 KEEPS SCL LOW 6.8s MAX tACQ tCONV 1, CH ADD, 10b/12b, RESULT (4 MSBs) ACK RESULT (8 LSBs) ACK STOP
Figure 11. Example of a Single Conversion Using the Internal Clock, SCAN = 1,1
R/W START ADDRESS FROM THE MASTER 1 ACK CONVERSION 1 tACQ tCONV 6.8s MAX tACQ MAX1363/MAX1364 KEEPS SCL LOW CONVERSION 2 tCONV
MAX1363/MAX1364 KEEPS SCL LOW CONVERSION N tACQ tCONV
1, CH ADD, 10b/12b, RESULT (4 MSBs)
ACK
RESULT 1 (8 LSBs)
ACK
1, CH ADD, 10b/12b, RESULT (4 MSBs)
ACK
RESULT N (8 LSBs)
ACK
STOP
Figure 12. Example of Scan-Mode Conversions Using the Internal Clock, SCAN = 0,0 and 0,1
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17
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
MAX1363/MAX1364
START
ADDRESS FROM THE MASTER
1
ACK
1, CH ADD, 10b/12b RESULT (4 MSBs) tACQ
ACK
RESULT (8 LSBs)
ACK tACQ
CONVERSION 1
1, CH ADD, 10b/12b, RESULT (4 MSBs) tACQ
ACK
RESULT N (8 LSBs)
ACK tACQ
CONVERSION N
Figure 13. Example of Scan-Mode Conversions Using the External Clock, SCAN = 0,0 and 0,1
When the MAX1363/MAX1364 receive a NACK, they release SDA allowing the master to generate a STOP or a repeated START condition.
8) If there is still an active fault, the device asserts INT again. See step 1. Writing SCAN1 and SCAN0 bits = [1,0] in the configuration byte activates monitor mode. The MAX1363/ MAX1364 scan from channels 0 up to the channel selected by [CS1:CS0] at a rate determined by the scan delay bits. The MAX1363/MAX1364 compare the conversion results with the lower and upper thresholds for each channel. When any conversion exceeds the threshold, the MAX1363/MAX1364 assert an interrupt by pulling INT low (if enabled). The MAX1363/ MAX1364 set the corresponding flag bit in the alarmstatus register and write conversion results to the latched-fault register to record the event causing the alarm condition. INT active state is randomly delayed with respect to the conversion. Depending on the number of channels scanned and the position in the channel scan sequence, the maximum possible delay for asserting INT is five conversion periods (37.5s typ, Delay = 0,0,0). Configuring Monitor Mode To write monitoring setup data, set the monitor-setup bit (bit 0 in setup byte) to 1 to extend writing up to 104 bits (13 bytes) of monitoring setup data. The number of bits written to the MAX1363/MAX1364 depends on whether the part is in single-ended or differential mode and whether the upper channel limit is set by [CS1:CS0] (Table 9). Terminate writing at any time by using a STOP or repeated START condition. Previous monitoring setup data not overwritten remains valid. A 1 written to the reset alarm CH_ clears the alarm, otherwise no action occurs (Table 10). Deassert INT by
Monitor Mode
Monitor-Mode Overview The MAX1363/MAX1364 automatically monitor up to four input channels. For systems with limited I2C bandwidth, monitor mode allows the C to set a window by programming lower and upper thresholds during initialization, and only intervening if the MAX1363/MAX1364 detect an alarm condition. This allows an interrupt-driven approach as an alternative to continuously polling the ADC with the C. Monitor mode reduces processor overhead and conserves I2C bandwidth. The following shows an example of events in monitor mode: 1) Fault condition(s) detected, INT asserted. 2) Host C services interrupt and sends SMBus alert to identify the alarming device. The MAX1363/ MAX1364 respond with the I2C slave address, pending arbitration rules. (See the SMBus Alert section.) 3) The MAX1363/MAX1364 release the INT. 4) Host C reads the alarm-status register, latchedfault register, and current-conversion results to determine the alarming channel(s) and course of action. 5) Host C services alarm(s); adjusts system parameters as needed and/or adjusts lower and upper thresholds. 6) Host C resets the alarming channel. See the Configuring Monitor Mode section. 7) Monitor mode resumes.
18
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4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
MAX1363/MAX1364
Table 9. Monitor-Mode Setup Data Format
Alarm reset, scan speed, INT_EN , (8 bits) AIN0 thresholds (24 bits) AIN1 thresholds (skip if differential mode, or CS1, CS0 < 1) (24 bits) AIN2 thresholds (skip if CS1, CS0 < 2) (24 bits) AIN3 thresholds (skip if differential mode, or CS1, CS0 < 3) (24 bits)
Table 10. Alarm Reset, Scan Speed Register, and INT_EN Data Format
RESET RESET RESET RESET ALARM CH 0 ALARM CH 1 ALARM CH 2 ALARM CH 3 0/1 0/1 0/1 0/1 DELAY 2 0/1 DELAY 1 0/1 DELAY 0 0/1 INT_EN 0/1
Table 11. Delay Settings
DELAY 2 DELAY 1 DELAY 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MONITOR-MODE CONVERSION RATE (ksps) 133.0* 66.5 33.3 16.6 8.3 4.2 2.0 1.0
clearing all alarms or by initiating an SMBus alert during an alarm condition (see the SMBus Alert section). The Delay 2, Delay 1, Delay 0 bits set the speed of monitoring by changing the delay between conversions. Delay 2, 1, 0 = 000 sets the maximum possible speed; 001 divides the maximum speed by ~2. Increasing delay values further divides the previous speed by two. INT_EN controls the open-drain INT output. Set INT_EN to 1 to enable the hardware interrupt. Set INT_EN to 0 to disable the hardware interrupt output. The INT output tri-states when disabled or when there are no alarms. The master can also poll the alarm status register at any time to check the alarm status. Repeat clocking channel threshold data up to the channel programmed by CS1 and CS0 (Table 12). For differential input mode, omit odd channels; the lower and upper threshold data applies to channel pairs. There is no need to clock in dummy data for odd (or even) channels (Table 6). To disable alarming on a specific channel, set the lower threshold to 0x800 and the upper threshold to 0x7FF for
*When using delay = [0,0,0] in internal reference mode and AIN3/REF configured as a REF output, the MAX1363/MAX1364 may exhibit a code-dependent gain error due to insufficient internal reference drive. Gain error caused by this phenomenon is typically less than 1%FSR (0.1F CREF) and increases with a larger CREF. Avoid this gain error by using an external reference, VDD, as a reference or use an internal reference with AIN3/REF as an analog input (see Table 4). Alternatively, choose delay bits other than [0,0,0] to lower the conversion rate.
Table 12. Lower and Upper Threshold Data Format
BYTE 1 2 3 B7 LT11 (MSB) LT3 UT7 B6 LT10 LT2 UT6 B5 LT9 LT1 UT5 B4 LT8 LT0 (LSB) UT4 B3 LT7 UT11 (MSB) UT3 B2 LT6 UT10 UT2 B1 LT5 UT9 UT1 B0 LT4 UT8 UT0 (LSB) ACKNOWLEDGE ACK ACK ACK
X = Don't care. ACK = Acknowledge.
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19
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
MAX1363/MAX1364
Table 13. Readback-Mode Format
ALARM RESET/SCAN SPEED 1 1 1 1 D2 D1 D0 INT AIN1 THRESHOLDS AIN0 AIN2 THRESHOLDS (SKIP IF DIFFERENTIAL THRESHOLDS (SKIP IF CS1, CS0 < 2) MODE OR CS1, CS0 < 1) 24 bits 24 bits 24 bits AIN3 THRESHOLDS (SKIP IF DIFFERENTIAL MODE OR CS1, CS0 < 3) 24 bits
Table 14. Reading in Monitor-Mode Data Format
ALARM-STATUS REGISTER 8 bits LATCHED-FAULT REGISTER 16, 32, 48, or 64 bits CURRENT-CONVERSION RESULTS 16, 32, 48, or 64 bits
Table 15. Alarm-Status Register
CH0 UP 0/1 CH0 LOW 0/1 CH1 UP 0/1 CH1 LOW 0/1 CH2 UP 0/1 CH2 LOW 0/1 CH3 UP 0/1 CH3 LOW 0/1
0 = Not-alarm condition. 1 = Alarm condition.
Table 16. Latched-Fault and CurrentConversion Register
AIN0 16-bit read AIN1 16-bit read AIN2 16-bit read AIN3 16-bit read
bipolar mode, or set the lower threshold to 0x000 and the upper threshold to 0xFFF for unipolar mode.
Readback Mode
Select readback mode by setting CS3, CS2 to [1,1] in the configuration byte. Begin a read operation to start reading back monitor-setup data. Clock out delay bit settings, INT_EN bit, and the lower and upper thresholds programmed for each channel. Readback mode follows exactly the same format as writing to the monitor-setup data, with the exception of the first 4 alarmreset bits, which are always 1 (Table 13).
Reading in Monitor Mode
Reading in monitor mode reads back the alarm-status register, latched-fault register, and current-conversion results as shown in Table 14. The MAX1363/MAX1364 register pointer loops back to the beginning of the current-conversion result after reading the last conversion result. Stop reading at any time by asserting a STOP condition or NACK. Note: The MAX1363/MAX1364 do not update the current-conversion results register while reading in monitor mode. Monitor mode resumes after a STOP condition or NACK.
20
Alarm-Status Register and Latched-Fault Register The latched-fault register records a snapshot of the alarming channel at the instance that a fault condition is asserted. An alarm-status bit of 1 (Table 15) indicates a fault, and the data in the latched-fault register of the corresponding channel contains the conversion result that caused the alarm to trip. Resetting alarms does not clear the latched-fault register, thus the latched-fault register contains valid data only if an alarm status bit is high for the given channel. The current-conversion register contains the most recent conversion results. If the user attempts to read past the last result of the current-conversion register, the MAX1363/MAX1364 wraps back to the beginning of the current-conversion result. The latched-fault register and current-conversion register follow the data format in the Reading a Conversion (Read Cycle) section. Register length depends on the number of conversions in one monitoring sequence. For example, when channel pairs 0/1 and channels 2/3 are monitored differentially, there are only two conversion results to report. The latched-fault register is 2 x 16 bits long, after which two current-conversion results follow. Likewise, if CS0 and CS1 limit the upper bound of the channel scan range from CH0 to CH2 in single-ended mode, the latched-fault register clocks out 3 x 16 bits of data followed by the current-conversion results, also 3 x 16 bits.
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4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
Resetting Alarm
Reset alarms by writing to monitor-setup data. See the Configuring Monitor Mode section and Table 10.
Transfer Functions
Output data coding for the MAX1363/MAX1364 is binary in unipolar mode and two's complement in bipolar mode with 1 LSB = VREF / 2N, where N is the number of bits. Code transitions occur halfway between successive-integer LSB values. Figures 14 and 15 show the transfer functions for unipolar and bipolar operations, respectively.
MAX1363/MAX1364
SMBus Alert
The SMBus-alert feature provides a quick method to identify alarming devices on a shared interrupt. Upon receiving an interrupt signal, the host C can broadcast a receive byte request to the alert-response slave address (0001100). Any slave device that generated an interrupt attempts to identify itself by putting its own address on the bus. The alert response can activate several different slave devices simultaneously. If more than one slave attempts to respond, bus arbitration rules apply, and the device with the lower address wins as a consequence of the open-collector bus. The losing device does not generate an acknowledgement and continues to hold the alert line low until serviced. Successful reading of the alert response address deasserts INT. When the MAX1363/MAX1364 successfully send the I2C address, it can resume and reassert INT right away (if the fault is still present). To prevent this from happening, monitor mode does not resume until after the host controller resets the alarm in the alarm status register. Any alarms not cleared when the device resumes monitor mode reassert INT.
Layout, Grounding, and Bypassing
Only use PC boards. Wire-wrap configurations are not recommended since the layout should ensure proper separation of analog and digital traces. Do not run analog and digital lines parallel to each other, and do not layout digital signal paths underneath the ADC package. Use separate analog and digital PC board ground sections with only one star point (Figure 16). High-frequency noise in the power supply (VDD) could influence the proper operation of the ADC's fast comparator. Bypass VDD to the star ground with a network of two parallel capacitors, 0.1F and 4.7F, located as close as possible to the MAX1363/MAX1364 power supply. Minimize capacitor lead length for best supply noise rejection. For extremely noisy supplies, add an attenuation resistor (5) in series with the power supply.
OUTPUT CODE 111...111 111...110 FS = REF + GND ZS = GND
FULL-SCALE TRANSITION
OUTPUT CODE 011...111 011...110 V FS = REF + AIN2 ZS = AIN-FS = -VREF + AIN2 V 1 LSB = REF 1024
100...010 100...001 100...000 011...111 011...110 011...101 1 LSB = VREF 1024
000...010 000...001 000...000 111...111 111...110 111...101
000...001 000...000 0 (GND) 1 512 INPUT VOLTAGE (LSB) FS - 0.5 LSB
100...001 100...000 -FS + 0.5 LSB V AIN- REF 2 AININPUT VOLTAGE (LSB) +FS - 1 LSB
Figure 14. Unipolar Transfer Function
Figure 15. Bipolar Transfer Function 21
______________________________________________________________________________________
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
MAX1363/MAX1364
SUPPLIES GND
3V OR 5V
VLOGIC = 3V/5V
R* = 5
4.7F
0.1F VDD GND 3V/5V DGND
the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNR (MAX)[dB] = 6.02dB x N + 1.76dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
MAX1363 MAX1364
DIGITAL CIRCUITRY
*OPTIONAL
Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to RMS equivalent of all other ADC output signals. SINAD(dB) = 20 x log (SignalRMS / NoiseRMS)
Effective Number of Bits
Figure 16. Power-Supply Grounding Connection
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The MAX1363/MAX1364's INL is measured using the endpoint method.
Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. With an input range equal to the ADC's full-scale range, calculate the ENOB as follows: ENOB = (SINAD - 1.76) / 6.02 SignalRMS SINAD(dB) = 20 x log NoiseRMS + THDRMS
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of the input signal's first five harmonics to the fundamental itself. This is expressed as: 2 2 2 2 V2 + V3 + V4 + V5 THD = 20 x log V1 where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples.
Aperture Delay
Aperture delay (tAD) is the time between the falling edge of the sampling clock and the instant when an actual sample is taken.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest distortion component.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of
22
______________________________________________________________________________________
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
Pin Configuration
TOP VIEW
AIN0 1 AIN1 AIN2 AIN3/VREF A0 2 3 4 5 10 VDD 9 GND SDA SCL INT
ANALOG INPUTS 2k AIN3/REF CREF 0.1F 3V/5V 3V/5V RP C SDA SCL INT GND RP RP AIN0 AIN1 AIN2 MAX1363 MAX1364 0.1F
Typical Operating Circuit
3V/5V 4.7F
MAX1363/MAX1364
VDD INT SDA SCL *RS *RS
MAX1363 MAX1364
8 7 6
MAX
*OPTIONAL
Ordering Information/Selector Guide (continued)
PART MAX1364EUB MAX1364LEUB* MAX1364MEUB TEMP RANGE -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 10 MAX 10 MAX 10 MAX I2C SLAVE ADDRESS 0110100/0110101 0110010/0110011 0110110/0110111 SUPPLY VOLTAGE (V) 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5
*Future product--contact factory for availability.
______________________________________________________________________________________
23
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response
MAX1363/MAX1364
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
e
10
4X S
10
INCHES MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 0.120 D1 0.116 0.118 D2 0.114 E1 0.116 0.120 0.118 E2 0.114 0.199 H 0.187 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S 0 6
MILLIMETERS MAX MIN 1.10 0.05 0.15 0.75 0.95 2.95 3.05 2.89 3.00 2.95 3.05 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0 6
H
O0.500.1
0.60.1
1
1
0.60.1
TOP VIEW
BOTTOM VIEW
D2 GAGE PLANE A2 A b A1 D1
E2
c
E1 L1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0061
1 1
I
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
10LUMAX.EPS

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